1. Field of the Invention
This invention relates generally to an electrically rewritable non-volatile semiconductor memory device and, more particularly, to page copy control methods thereof.
2. Description of Related Art
Electrically rewritable nonvolatile semiconductor memories include a flash memory of the so-called NAND type. In this NAND type flash memory, a technique for performing page copy operations has already been proposed. A page copy operation is for writing or programming cell data of a page into another page. What are mainly required for achieving such copy writing functionality are: (1) speed-up of write data transfer rate, and (2) higher reliability of copy writing.
The speedup or acceleration of the copy operation is achievable by designing a page copy as an on-chip operation of a NAND flash memory. More specifically, a high-speed copy operation is made possible by reading data of a first page of a memory cell array to a sense amplifier and then writing the read data into a second page without outputting the read data to external terminals (for example, see U.S. Pat. No. 5,465,235). This scheme is capable of shortening the length of a write processing time period because of that the read data is not output to outside of a chip; however, the scheme is incapable of eliminating risks as to unwanted data alteration or corruption occurring when repeating copy write operations.
On the other hand, the reliability of copy writing can be guaranteed by letting the read data of a sense amplifier be output toward the outside of the chip. This can be said because such sense-amp data output permits an externally provided memory controller to perform inspection or testing of write data. Unfortunately in this case, the resulting write data transfer rate becomes sacrificed significantly.
FIG. 23 shows an exemplary copy write operation which is designed to output read data to the chip outside. Shown herein is an example of a per-page repeated copy operation which includes the steps of reading data of a page address Row1, writing the data into a page address RowA, sequentially reading data of a page address Row2, and writing the data into a page address RowB.
The data readout of the page address Row1 is performed in receipt of a read command “Read com.” input and an address “Add.(Row1)” input. During a data read operation of from the memory cell array to sense amplifier, the memory chip is set in a busy state. “Data Out(Row1)” indicates such an operation that a page of data of the address Row1 read to the sense amp are serially transferred by a read enable signal REB and then output toward the chip outside.
The data output to the chip outside is then tested by a memory controller. And, sequentially inputting a load command “Load com.”, address “Add.(RowA)”, additional or extra write data “Data(extra)” and write command “Prog. Com.” results in that a write operation to the page address RowA is performed. During this write operation, the memory is in a busy state. If any data modification or correction is not necessary, it is no longer required to perform any extra data input from the outside. Additionally, the extra data may alternatively be partially modified data or one page of data. The extra data is overwritten onto the read data being presently held in a page buffer and then used as corrected write data. After completion of the write operation to the page address RowA, data reading of the page address Row2 and writing of such read data into the page address RowB are performed in a similar way.
With the prior art copy writing scheme stated above, whenever an attempt is made to guarantee the reliability, a control technique becomes inevitable for outputting the read data to the chip outside and performing the next read operation after having completed a write operation as shown in FIG. 23. In this scheme, a serial output time taken for copy data check becomes a significant factor or cause which deteriorates the high speed performance of the copy operation. A more detailed explanation is as follows. When the data read time of from the memory cell array to the sense amplifier is set at 25 microseconds (μsec), the memory cell array's data writing time is 200 μsec, the page length is 2 kilobytes (kB), and the cycle of serial transfer of sense amp data to the chip outside is 50 nanoseconds (nsec), the transfer rate is calculated as 6.2 megabytes per second (MB/sec). This is in the case of ignoring a data adding time during copy operations. For speedup of the write transfer rate, the read data's serial output time period (50 nsec×2 k=100 μsec) becomes a large overhead.